TSMC technical article 016
A13 Logic Technology
How TSMC extends its A14 nanosheet platform through optical scaling, compatible design rules and design-technology co-optimisation—and what remains undisclosed before planned 2029 production.01
What it is
TSMC A13 is a planned advanced logic process derived directly from the A14 nanosheet platform. It applies a 97% optical shrink and further design-technology co-optimisation to make an equivalent A14 design smaller while preserving compatible design rules.
TSMC reports a 6% die-area saving relative to A14 and additional performance and power-efficiency gains whose magnitudes are not yet published. A13 is scheduled for volume production in 2029 and is intended for next-generation AI, high-performance computing and mobile processors. It is a manufacturing technology, not a processor architecture or a finished chip.
Base platformA14 familyNanosheet logic
Optical scale97%Linear shrink from A14
Area6% smallerEquivalent die design
Production2029TSMC schedule
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Position in TSMC’s logic roadmap
| Technology | Relationship | Published distinction | Production |
|---|---|---|---|
| N2 | First-generation TSMC nanosheet platform | Reference node used for A14’s published PPA comparison | Volume production began Q4 2025 |
| A16 | N2-family performance extension | Nanosheets plus Super Power Rail backside power delivery | Scheduled H2 2026 |
| A14 | Full-node successor to N2 | Up to 15% faster, up to 30% lower power or more than 20% higher logic density than N2 | Scheduled 2028 |
| A13 | Direct A14-family shrink | 97% optical scale, 6% die-area saving and compatible design rules | Scheduled 2029 |
| A12 | Separate A14 platform enhancement | Second-generation Super Power Rail for AI and HPC | Scheduled 2029 |
Do not add unrelated comparisons. TSMC has published A14-versus-N2 PPA figures and A13-versus-A14 area saving. It has not published a complete A13-versus-A14 speed, power or density table.
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How the 97% optical shrink saves 6% area
An optical shrink reduces selected layout dimensions while retaining the parent platform’s basic design framework. A smaller implementation can place the same logical design in less silicon area, or use the recovered area for additional functions. Actual product results still depend on cell choice, analogue blocks, SRAM, I/O, routing congestion and design margins; an entire chip will not necessarily shrink uniformly by exactly 6%.
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Nanosheet transistor foundation
| Element | Function | A13 disclosure |
|---|---|---|
| Nanosheet channels | Carry current between source and drain. | Inherited from the A14 nanosheet platform; geometry unpublished. |
| Gate-all-around control | Electrostatically controls the channel from several surfaces. | Architecture family confirmed; materials and dimensions unpublished. |
| Standard cells | Combine transistors into reusable logic functions. | A14 uses NanoFlex Pro; the exact A13 library configuration is not published. |
| Interconnect stack | Connects cells into complete circuits. | Metal count, pitches, materials and resistance are unpublished. |
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What backward-compatible design rules enable
- Start from an A14 implementation.The design already follows A14 layout rules and uses qualified cells and IP.
- Adopt the A13 process kit.Compatible rules reduce rule changes and support smoother IP migration; they do not eliminate revalidation.
- Rescale and re-characterise.Libraries, memories and physical blocks are mapped to A13 while timing, power and reliability models are updated.
- Repeat physical design.Placement, clocking and routing are optimised for the smaller geometry and the product’s performance target.
- Verify sign-off.Design-rule, timing, power-integrity, thermal and manufacturability checks must pass against A13 models.
- Tape out and qualify silicon.Masks are generated, test chips or products are fabricated, and measured silicon is validated before volume production.
Compatibility is not automatic portability. Analogue IP, SRAM, high-speed interfaces and large custom blocks may require specific A13 qualification even when the top-level rule framework is compatible.
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From design to manufactured die
| Stage | What happens | Evidence boundary |
|---|---|---|
| Design and masks | Verified circuit layouts are converted into the mask set used to pattern wafer layers. | Generic foundry workflow; A13 mask count is unpublished. |
| Front-end fabrication | Repeated deposition, lithography, etch and implantation form isolation, nanosheet channels, gates and contacts. | TSMC confirms nanosheets, not the complete A13 process sequence. |
| Back-end interconnect | Multiple metal and dielectric layers connect transistors into logic, memory and I/O circuits. | A13 interconnect materials and pitches are unpublished. |
| Wafer test | Electrical probing identifies functional die and measures process behaviour. | A13 yield and defect density are unpublished. |
| Assembly and package | Known-good die are cut and attached to the product’s selected package or 3D integration flow. | Packaging is product-specific; A13 does not prescribe one package. |
| Final qualification | Packaged devices undergo electrical, reliability and application testing. | No A13 customer product has reached volume production. |
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Where A13 fits
| Application | Why scaling matters | What A13 does not define |
|---|---|---|
| AI accelerators | More logic per die and better energy efficiency can increase compute within area and power limits. | Matrix architecture, memory type, package and interconnect. |
| HPC processors | Smaller logic can support more cores, cache or specialised engines within a reticle-constrained design. | Core count, clock frequency, chiplets and system topology. |
| Mobile SoCs | Area and efficiency can improve on-device AI and battery-limited computation. | CPU, GPU, NPU, modem and product power. |
A13 manufactures customer designs. Its value appears only after a chip designer combines the process with an architecture, memories, physical IP, packaging and software. TSMC’s 2029 packaging roadmap—including large CoWoS and A14-to-A14 SoIC—is adjacent context, not an announced A13 package specification.
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Manufacturing context videos
These videos explain semiconductor fabrication and fab operations. Only the TSMC Fab Tour is published by a TSMC organisation; none provides A13 design rules or device specifications.
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Terms
- A13
- TSMC’s A14-family logic process scheduled for 2029 production.
- Optical shrink
- Reduction of selected layout dimensions using a compatible process framework.
- Nanosheet
- Horizontal transistor channel surrounded by the gate.
- GAA
- Gate-all-around transistor structure.
- DTCO
- Joint optimisation of process technology and circuit design.
- PPA
- Performance, power and area.
- PDK
- Process design kit containing rules, models and design enablement data.
- Tape-out
- Release of a verified chip design for mask generation and fabrication.
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Limits of the evidence
- A13 is a pre-production technology; specifications and schedules may change before 2029.
- TSMC has disclosed a 6% die-area saving but no numerical A13-versus-A14 speed or power gain.
- Transistor dimensions, SRAM density, metal stack, voltages, yield and defect density are unpublished.
- The A13 name is a technology designation, not proof that every feature measures 13 angstroms.
- Backward-compatible rules reduce migration effort but do not remove implementation, sign-off or silicon qualification.
- A12’s backside power delivery is a separate platform enhancement and must not be attributed to A13 without further disclosure.
- The embedded videos provide manufacturing context; they are not evidence for A13 specifications.
- Price, wafer cost, customer identity and unofficial performance estimates are excluded.
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Primary sources
- TSMC debuts A13 at the 2026 North America Technology SymposiumPrimary A13 announcement: A14 relationship, area saving, compatibility, applications and production schedule.
- TSMC 2026 Technology Symposium releaseOfficial PDF copy of the A13 announcement and adjacent technology roadmap.
- TSMC A14 technologyA14 nanosheet foundation, NanoFlex Pro, N2 comparison and 2028 production plan.
- TSMC A16 technologyNanosheet and Super Power Rail platform boundary.
- TSMC unveils A14Original A14 platform announcement and published N2-relative PPA boundaries.
- TSMC 2 nm technologyN2 nanosheet foundation and current volume-production status.