Qualcomm technical article 014
Dragonfly C1000 Data-centre CPU
How Qualcomm’s planned 250-plus-core server processor uses custom Oryon cores, a modular chiplet design, PCIe 7 and CXL to host general-purpose and AI infrastructure workloads.01
What it is
Qualcomm Dragonfly C1000 is a planned Arm-compatible data-centre CPU built from more than 250 custom Oryon cores and multiple chiplets. It is designed to run general-purpose cloud work, coordinate agentic services and act as the host processor for external AI accelerators.
C1000 is a CPU, not Qualcomm’s Dragonfly AI200, AI250 or AI300 inference accelerator. Its function in an AI rack is to prepare data, run operating-system and service code, schedule work, drive storage and networking, and keep attached XPUs supplied through high-bandwidth I/O. Commercial availability is expected in 2028.
CPU250+ coresCustom Qualcomm Oryon
Frequency>5 GHzPublished design target
I/O>2 TB/sPCIe Gen 7 plus CXL
AvailabilityExpected 2028Pre-commercial roadmap
02
Three CPU workload roles
| Role | Primary work | Design pressure |
|---|---|---|
| Agentic CPU | Runs orchestration, tool calls and interactive services around AI agents. | High request throughput plus low per-request latency. |
| General-purpose CPU | Runs cloud, enterprise and first- or third-party server workloads. | Core density, per-core response and flexible vCPU allocation. |
| AI head-node CPU | Hosts and feeds external GPUs or other XPUs. | Low host overhead and very high I/O bandwidth to maximise accelerator use. |
| CPU inference | Executes suitable inference directly on Oryon cores and vector resources. | Memory bandwidth and vector efficiency without a separate accelerator. |
03
Chiplet architecture
Chiplets let Qualcomm scale core count and I/O without manufacturing one monolithic die. Compute and I/O functions can be partitioned across dies and joined in an advanced package. This improves modularity, but performance still depends on the latency, bandwidth and coherency of the internal fabric—figures Qualcomm has not yet released.
04
How it hosts an AI workload
- Accept and prepare requests.Oryon cores run services that authenticate, tokenise, batch and route incoming inference work.
- Allocate compute.Scheduler and runtime code select CPU resources or an attached XPU according to model and latency requirements.
- Move operands.The memory subsystem supplies CPU work; PCIe 7 and CXL carry data to accelerators, network adapters or disaggregated memory.
- Coordinate execution.Head-node processes launch kernels, handle collective setup and overlap I/O with accelerator computation.
- Process service logic.CPU cores execute agent orchestration, retrieval, control flow and operations that do not fit the accelerator.
- Return and monitor results.Telemetry, error handling and infrastructure software track service health and recover failed components.
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I/O, memory and reliability
| Subsystem | Published design | Purpose |
|---|---|---|
| PCIe | Generation 7; more than 2 TB/s aggregate connectivity | Links accelerators, high-speed network adapters and storage. |
| CXL | Supported; version and lane allocation not published | Coherent accelerator attachment and memory expansion or disaggregation. |
| Memory | Leading-edge low-power server memory; capacity, channels and rate undisclosed | Supplies more than 250 cores while controlling power and field-service requirements. |
| Optional HBC | CPU inference may attach Qualcomm High Bandwidth Compute | Adds near-memory compute and bandwidth for suitable inference. |
| RAS | ECC, fault isolation and error recovery | Contains faults and maintains service in large deployments. |
| Confidential computing | Supported; implementation detail not published | Protects workloads and data while in use. |
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From CPU to rack
| Layer | Component | Function |
|---|---|---|
| Processor | Dragonfly C1000 | General-purpose, agentic and AI head-node compute. |
| Accelerator | Dragonfly AI200 / AI250 / AI300 or third-party XPU | High-throughput model inference. |
| Data movement | PCIe 7, CXL, 800G / 1.6T optical and electrical connectivity | Scale-up, scale-out, storage and campus links. |
| Rack | OCP ORv3-compliant air- or liquid-cooled servers | Power, cooling, serviceability and dense deployment. |
| Management | Dragonfly AI Infrastructure Management Suite | Provisioning, monitoring, orchestration and fault handling. |
07
Roadmap and deployment status
Qualcomm announced C1000 on 24 June 2026 and expects commercial availability in 2028. Meta has a multi-generation agreement under which C1000 is planned for its next-generation server fleet. This is design and customer-intent evidence, not evidence of shipping production silicon.
| Item | Published state | What it does not establish |
|---|---|---|
| C1000 silicon | Announced; expected commercial availability in 2028. | Final clocks, power, yield, price or delivered performance. |
| Meta agreement | Planned next-generation server deployment. | Volume, configuration or deployment date. |
| >2× performance per watt | Qualcomm estimate based on specifications and existing benchmarks. | Independent system measurement. |
| OCP ORv3 support | Air- and liquid-cooled rack compatibility planned. | A single fixed server or rack configuration. |
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Terms
- Chiplet
- One die combined with other dies in a single package.
- Head node
- CPU host that prepares and controls accelerator work.
- XPU
- Generic term for GPU or another specialised accelerator.
- CXL
- Cache-coherent link layered on PCIe physical signalling.
- RAS
- Reliability, availability and serviceability functions.
- ECC
- Error-correcting code for detecting and correcting data faults.
- HBC
- Qualcomm High Bandwidth Compute near-memory architecture.
- ORv3
- Open Rack version 3 specification from the Open Compute Project.
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Limits of the evidence
- C1000 is a 2028 roadmap product; specifications may change before commercial release.
- The exact core count, process node, socket power, cache hierarchy and instruction extensions are unpublished.
- Memory type, channels, capacity and raw bandwidth are not yet disclosed.
- The greater-than-2-TB/s I/O figure is aggregate PCIe 7 connectivity, not application data throughput.
- Qualcomm’s comparative efficiency and TCO claims are estimates, not independent measurements, and are excluded from conclusions.
- The Meta agreement does not disclose deployment volume or system configuration.
- Price and promotional material are excluded.
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Sources
- Qualcomm Dragonfly C1000 product pageCurrent features, workload roles, I/O, memory and RAS disclosures.
- Qualcomm data-centre roadmap announcementC1000 architecture, portfolio context, availability and Meta agreement.
- Qualcomm Data Center overviewRack-scale portfolio and system-layer relationships.
- Dragonfly product catalogueCPU, accelerator and connectivity product boundaries.