Intel technical article 010
Xeon 6+ E-core / Clearwater Forest
How Intel’s 144- to 288-core server CPUs combine Intel 18A E-core compute tiles, 3D hybrid bonding, twelve-channel DDR5 memory and a two-socket platform.01
What it is
Intel Xeon 6+ is a four-SKU family of high-density server processors built around Efficient-cores. Formerly codenamed Clearwater Forest, it scales from 144 to 288 physical cores per socket, one thread per core, and supports one- or two-socket systems.
Xeon 6+ is intended for throughput-oriented services such as cloud-native applications, web serving, microservices, network functions, storage and consolidated virtual machines. Its E-cores trade the large per-core structures and simultaneous multithreading of a P-core design for more independent cores within a socket and power envelope. It is also Intel’s first launched server processor to use Intel 18A compute silicon.
Family6960E+ to 6990E+Four launched SKUs
Core range144–288 E-coresOne thread per core
ProcessIntel 18A computeRibbonFET + PowerVia
Platform1S / 2SFCLGA7529 socket
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Why E-cores exist in Xeon
Server workloads do not all need the highest possible performance from one thread. A fleet may instead run thousands of independent requests, containers or virtual CPUs. For those workloads, total useful work per socket can depend more on core count, memory bandwidth and scheduling density than on a wide, power-hungry individual core.
Intel therefore maintains two Xeon paths. P-core products retain larger cores, simultaneous multithreading and instruction features for per-thread, AI and HPC work. E-core products target parallel service throughput with many single-threaded cores. Xeon 6+ extends that E-core path to 288 cores while preserving server memory, I/O, security and acceleration blocks.
| Design choice | What it provides | Trade-off |
|---|---|---|
| Many E-cores | More independently scheduled workers per socket. | Lower peak capability per individual core than a large P-core design. |
| No SMT | One visible thread owns each physical core. | No second logical thread to fill otherwise idle execution slots. |
| Large shared platform | Twelve memory channels, 96 PCIe lanes and two-socket support. | Memory and I/O remain shared resources across hundreds of cores. |
| On-chip accelerators | Offload compression, crypto, data movement and load balancing. | Software must use the relevant APIs and supported operations. |
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3D chiplet architecture
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How a service request executes
- Schedule a core.The operating system assigns a runnable software thread to one physical E-core.
- Fetch instructions and data.The core checks private and shared caches before the memory controllers access DDR5.
- Execute general code.Integer, branch and vector pipelines process the service without an SMT sibling sharing the core.
- Use an accelerator where supported.QAT, DSA, DLB or IAA can handle selected crypto, compression, movement, scheduling or analytics operations.
- Reach external devices.PCIe connects network and storage endpoints; UPI maintains coherency between two sockets.
- Run many copies.Throughput scales by distributing independent requests or virtual machines across many cores, subject to shared memory and I/O limits.
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Launched processor family
| Processor | Cores / threads | Base / max turbo | Cache | TDP |
|---|---|---|---|---|
| Xeon 6960E+ | 144 / 144 | 2.4 / 3.2 GHz | 432 MB | 330 W |
| Xeon 6970E+ | 192 / 192 | 2.3 / 3.2 GHz | 480 MB | 400 W |
| Xeon 6980E+ | 264 / 264 | 2.1 / 3.2 GHz | 528 MB | 400 W |
| Xeon 6990E+ | 288 / 288 | 2.2 / 3.2 GHz | 576 MB | 450 W |
Frequency is not throughput. Base and turbo figures describe operating points under defined electrical and thermal conditions. A 288-core processor’s result depends on parallelism, vectorisation, memory traffic, software and sustained power—not core count multiplied by clock alone.
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Platform specifications
| Area | Published Xeon 6+ specification | Boundary |
|---|---|---|
| Compute silicon | Intel 18A; E-cores | Core-count and cache vary by SKU. |
| Packaging | Foveros Direct 3D and EMIB | Joins compute, active base and I/O silicon inside one package. |
| Memory | 12 channels; DDR5 RDIMM up to 8,000 MT/s at 1DPC | Maximum 1.5 TB per socket in Intel’s ARK record. |
| Socket scaling | One or two sockets | Up to six UPI links at 24 GT/s connect a two-socket system. |
| PCI Express | Gen 5; up to 96 lanes | Per processor; system wiring determines usable slots. |
| Vector instructions | AVX2 and Intel Deep Learning Boost | The E-core product does not expose the P-core family’s AVX-512/AMX path. |
| Integrated accelerators | Four each of QAT, DLB, DSA and IAA on 6990E+ | Published default-device count for the flagship SKU. |
| Security | TDX, SGX, TME-MK and control-flow enforcement | Deployment depends on platform firmware and software support. |
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Mechanisms beyond core count
| Mechanism | Function | Suitable work |
|---|---|---|
| Intel QAT | Offloads selected compression and cryptographic operations. | Network security, storage and data services. |
| Intel DSA | Moves and transforms data without occupying normal core pipelines. | Memory copies, virtualisation and storage paths. |
| Intel DLB | Balances queued events across worker cores. | Packet processing and event-driven services. |
| Intel IAA | Accelerates selected in-memory analytics and compression operations. | Databases and data pipelines with supported libraries. |
| Intel TDX | Creates hardware-protected virtual-machine trust domains. | Confidential cloud workloads. |
| Speed Select | Allows supported frequency, power and active-core operating profiles. | Deployment-specific balance between density and per-core rate. |
08
Terms
- E-core
- Intel Efficient-core, optimised for dense throughput.
- Intel 18A
- Intel process technology using RibbonFET and backside PowerVia delivery.
- Foveros Direct
- Fine-pitch hybrid bonding for stacked logic dies.
- EMIB
- An embedded bridge joining adjacent chiplets in one package.
- UPI
- Intel’s coherent processor-to-processor interconnect.
- 1DPC
- One memory DIMM populated per memory channel.
- SMT
- Multiple logical threads sharing one physical core; absent here.
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Limits of the evidence
- Product specifications are Intel-published values; system firmware and vendor designs determine final behaviour.
- Maximum memory speed requires the supported DIMM population and is not guaranteed for every capacity.
- Core count, cache, clock and TDP do not establish application performance.
- Integrated accelerators require compatible software and do not accelerate arbitrary code.
- The package diagram is a functional explanation; Intel has not published every internal connection rate in the cited product material.
- The embedded videos provide launch and event context, not evidence for the specification tables.
- Comparative benchmarks, consolidation claims and performance-per-watt claims are excluded.
- Price and promotional material are excluded.
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Sources
- Intel Xeon 6+ product familyCurrent four-SKU range, launch status and headline specifications.
- Intel Xeon 6990E+ specificationsFlagship core, memory, I/O, accelerator and security fields.
- Intel Xeon 6+ product briefClearwater Forest architecture and workload positioning.
- Intel Xeon 6+ product presentationPackage, platform and feature architecture.
- Intel advanced process technologies for data centresIntel 18A compute tiles, active base tiles and 3D packaging.
- Intel Xeon P-core and E-core architectureDifference between throughput-oriented E-cores and P-cores.
- Introducing the Intel Xeon 6+ processorOfficial Intel Business launch video supplied for this article.
- Computex 2026: Intel Xeon 6+, Diamond Rapids & More!Chips and Cheese event coverage supplied for additional context.