Intel technical article 017
Intel 14A
How Intel’s post-18A foundry process combines RibbonFET 2 transistors, direct-contact backside power, High-NA EUV and flexible standard cells—and where its published targets stop.What it is
Intel 14A is an advanced logic process in active development for Intel Foundry customers and a planned Intel product. It is the successor to Intel 18A, not a processor architecture or a finished chip.
The process combines second-generation gate-all-around transistors, direct-contact backside power delivery, selected High-NA EUV lithography and standard-cell options that let designers trade speed, power and area within one design. Intel’s published performance, power and density figures are development targets based on internal analysis; production silicon and customer products have not yet established them independently.
Published targets relative to Intel 18A
| Measure | Intel 14A target | Correct interpretation |
|---|---|---|
| Performance | 15–20% improvement at the same power | A design point modelled against Intel 18A; not a guaranteed clock-frequency gain for every chip. |
| Power | 25–35% reduction at the same performance | An alternative design point; it must not be added to the performance figure. |
| Density | up to 30% chip-density improvement | An upper-end design estimate; complete chips include SRAM, analogue, I/O and routing that scale differently. |
RibbonFET 2 transistor
| Element | What it does | What Intel has disclosed |
|---|---|---|
| Stacked ribbons | Provide several horizontal current-carrying channels within one device footprint. | Second-generation RibbonFET architecture; physical dimensions are unpublished. |
| Gate-all-around control | Places the gate around the channel surfaces to improve electrostatic control. | Architecture family confirmed; detailed device construction and materials are unpublished. |
| Source and drain | Inject and collect carriers through the channels when the transistor switches. | 14A contact geometry, resistance and drive-current data are unpublished. |
PowerDirect backside power delivery
Power and signals compete for routing space in a conventional front-side network. A backside power network supplies current from below the transistors, shortening parts of the power path and reducing congestion above them. Intel describes PowerDirect as an evolution of PowerVia with direct-contact power delivery. The company has not published a complete 14A power-grid stack, contact resistance or product-level efficiency result.
High-NA EUV lithography
| Property | Conventional EUV | High-NA EUV | Meaning for 14A |
|---|---|---|---|
| Numerical aperture | 0.33 NA | 0.55 NA | Higher NA can resolve smaller features at the same exposure wavelength. |
| Tool-level capability | Current production baseline | Up to 1.7× smaller features and 2.9× higher two-dimensional density | These are lithography-system capabilities, not published 14A chip-density results. |
| 14A use | Expected to remain in the process mix | Potential first use in high-volume logic manufacturing | Intel expects a mix of 0.33-NA, 0.55-NA and other patterning methods rather than High-NA on every layer. |
EUV lithography projects a circuit pattern onto photoresist using 13.5 nm light. Increasing numerical aperture improves optical resolution and can reduce the multiple-patterning steps otherwise needed for selected dense layers. Layer selection still depends on process capability, cost, overlay, mask design and manufacturing yield. Intel’s filings identify 14A as a potential first High-NA EUV high-volume logic node; they do not state that qualification or volume production is complete.
Turbo Cells: local PPA choices
| Design region | Cell choice | Purpose |
|---|---|---|
| Timing-critical path | Higher-performance cell | Improves speed where delay limits the whole circuit. |
| Power-sensitive logic | Lower-power cell | Reduces leakage or switching power where additional speed is unnecessary. |
| Area-constrained block | Reduced-area cell | Fits more logic into the block while accepting a different performance point. |
| Balanced logic | General-purpose cell | Provides the default compromise between speed, power and density. |
Standard cells are pre-designed logic building blocks used by automated design tools. Turbo Cells let a physical-design flow mix cell variants within the same block instead of imposing one uniform trade-off. Intel has described four variants and made the first available for pre-PDK exploration, but has not published a complete production library, cell dimensions or measured product result.
From process kit to production
- Early PDK.Lead customers receive preliminary design rules, transistor models and reference flows for exploration.
- EDA and IP enablement.Tool vendors and IP suppliers qualify synthesis, physical design, verification, memories and interfaces.
- Test chip.Customers and Intel tape out representative circuits to measure performance, power, yield and reliability.
- Process qualification.Manufacturing data must show stable operation, defect control and reliability across production conditions.
- Customer commitment.Product teams decide whether technical results, schedule, capacity and risk justify a production tape-out.
- Possible high-volume manufacturing.Only a qualified process with sufficient committed demand proceeds to sustained commercial production.
Current development and commercial status
| Period | Published position | What it establishes |
|---|---|---|
| April 2025 | Intel published its 14A PPA targets and technology features. | A development target and process direction, not production silicon. |
| 2025 | Early 14A PDK distributed to lead customers; several indicated an intention to build test chips. | Customer evaluation had begun. |
| February 2026 filing | Intel reported active development but no significant external customer secured for 14A. | Technical work continued while the external-foundry business case remained unproven. |
| March 2026 update | Intel said development remained on track after process simplification. | A management update, not independent qualification evidence. |
| H2 2026–H1 2027 | Intel expects prospective customers to make key manufacturing decisions. | A decision window, not a guaranteed production date. |
Intel’s earlier public roadmap placed 14A availability in 2027. The current evidence is more conditional: Intel says continued development and manufacturing investment are conditional on sufficient committed demand. Its 2026 annual filing states that the company may pause or discontinue pursuit of 14A if it cannot secure a significant external customer. Intel also plans an initial internal product and retains the option to offer that product through the foundry.
Where the process could be used
| Design class | Relevant 14A capability | What the process does not define |
|---|---|---|
| AI accelerators | Dense logic, high-speed cells and power delivery for compute-intensive blocks. | Matrix architecture, HBM interface, package and software. |
| Server CPUs | Performance and power options for cores, cache control and chiplet interfaces. | Core architecture, core count, cache size and platform. |
| GPUs | Parallel logic density and power routing across large compute arrays. | Shader design, memory system, clocks and graphics features. |
| Chiplets and custom silicon | Foundry process for customer-defined compute and control die. | Die partitioning, die-to-die link, package or workload. |
A process node supplies manufacturable transistors, wires, cells, memories and design rules. The customer still defines the chip architecture and system. No processor should be described as an Intel 14A product until Intel or the customer identifies it and production status is verified.
Videos
Terms
- 14A
- Intel’s post-18A advanced logic process; “A” denotes ångström-class naming, not one physical dimension.
- RibbonFET
- Intel’s gate-all-around transistor architecture using stacked ribbon-shaped channels.
- PowerDirect
- Intel’s direct-contact backside power-delivery architecture for 14A.
- High-NA EUV
- Extreme-ultraviolet lithography using a 0.55 numerical-aperture optical system.
- Turbo Cells
- Compatible standard-cell variants for local speed, power and area trade-offs.
- PDK
- Process design kit containing foundry rules, models and design-enablement data.
- PPA
- Performance, power and area.
- HVM
- High-volume manufacturing.
Limits of the evidence
- Intel 14A remains in development; specifications, schedule and commercial plans may change.
- The 15–20% performance, 25–35% power and up-to-30% density figures are Intel internal estimates relative to 18A.
- No independent 14A product benchmark, yield, defect-density or reliability dataset is public.
- Intel has not published transistor dimensions, complete design rules, SRAM density, metal stack or production operating voltages.
- High-NA EUV tool capability must not be confused with whole-chip scaling or applied to every process layer.
- Early PDK access and planned test chips do not establish qualification or high-volume manufacturing.
- As of Intel’s 2026 annual filing, no significant external 14A customer had been secured.
- Prices, wafer costs, customer rumours and unofficial performance claims are excluded.
Primary sources
- Intel Foundry process technology14A PPA targets, RibbonFET 2, PowerDirect and Turbo Cells.
- Intel Foundry Direct Connect 2025Early PDK distribution, lead-customer test-chip intent and technology description.
- Intel 2025 Form 10-K, filed February 2026Current development status, High-NA EUV plan, internal product and external-customer dependency.
- Intel Foundry progress and capital discipline, March 2026Process simplification, on-track statement and prospective customer decision window.
- Intel High-NA EUV press kit0.55-NA lithography capability, process integration and tool context.
- Intel Foundry: Turbo Cells introductionCell variants, local PPA trade-offs and pre-PDK availability.
- Intel Foundry for HPC and AI briefRibbonFET 2, PowerDirect and 14A-E roadmap context.