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AMD technical article 004

Ryzen AI Max 300 Series / Strix Halo

How AMD combines desktop-class Zen 5 CPU chiplets, a large integrated RDNA 3.5 GPU, an XDNA 2 NPU and a 256-bit unified memory interface in one PC processor.

01

What it is

Ryzen AI Max 300 is AMD’s high-end integrated processor family for mobile workstations, compact desktops and local AI systems. “Strix Halo” is its former codename. The package contains up to 16 Zen 5 CPU cores, up to 40 RDNA 3.5 graphics compute units and a 50-TOPS XDNA 2 neural processor.

Its defining feature is not one engine but the memory system around them. Up to 128 GB of LPDDR5X-8000 is attached through a 256-bit interface, and the CPU and integrated GPU address the same physical memory pool. Firmware can reserve up to 96 GB for graphics. This avoids a separate graphics card and its fixed local VRAM, although CPU and GPU still compete for bandwidth and capacity.

CPU8–16 Zen 5 coresSMT; up to 32 threads
Integrated GPU32 or 40 RDNA 3.5 CUsRadeon 8050S / 8060S
AI engine50 NPU TOPSXDNA 2
Memory256-bit LPDDR5XUp to 128 GB at 8000 MT/s
02

Why it exists

Thin workstations and local AI computers need more graphics capacity and memory than a conventional laptop processor, but a separate GPU adds another package, memory pool, board area and cooling path. Strix Halo puts a much larger GPU beside chiplet CPU cores and feeds both from a wide memory interface.

System constraintConventional arrangementStrix Halo response
Large local modelsModel must fit in fixed GPU VRAM or spill into slower host transfers.Up to 96 GB of the common memory pool can be assigned to graphics.
Mixed workloadsCPU, GPU and accelerator occupy separate chips and memory domains.CPU, GPU and NPU share one package and coherent system memory.
Compact chassisDiscrete graphics requires extra board space, power delivery and cooling.A large integrated GPU removes the separate graphics package.
Always-on AIRunning every neural task on CPU or GPU consumes general compute capacity.The NPU executes supported inference graphs at lower power.
03

Package architecture

Ryzen AI Max package architectureOne or two Zen 5 CPU chiplets connect to a large system die containing the Radeon GPU, XDNA NPU, media and I/O engines, which connects through a 256-bit interface to LPDDR5X memory. CPU CHIPLET 0Up to 8 Zen 5 coresL2 + shared L3 cache CPU CHIPLET 1Up to 8 Zen 5 coresAbsent on 8-core model SYSTEM DIE · TSMC 4 nmRadeon 8050S / 8060S32 / 40 RDNA 3.5 CUsXDNA 2 NPUUp to 50 TOPSMedia + displayAV1, DP 2.1, HDMI 2.1I/O controllerPCIe 4.0, USB4 256-bitSHARED MEMORYLPDDR5X-8000Up to 128 GB256 GB/s theoretical
The CPU chiplets and the larger system die form one package. The 8-core 385 uses one CPU chiplet; the 12- and 16-core models use two.
04

How a local AI workload runs

  1. Load once.Model weights are placed in LPDDR5X system memory rather than copied into a separate graphics memory pool.
  2. Reserve graphics memory.Firmware defines how much of the shared pool is exposed to the integrated GPU; AMD documents up to 96 GB.
  3. Prepare on the CPU.Zen 5 cores run the operating system, tokenisation, orchestration and unsupported operators.
  4. Execute the main graph.The GPU handles highly parallel kernels; supported power-sensitive inference graphs may run on the XDNA 2 NPU.
  5. Share results.Engines exchange buffers through system memory, reducing explicit device-to-device copies.
  6. Manage contention.Memory controllers arbitrate requests because CPU and GPU share the same finite bandwidth.
05

Current non-PRO line-up

ModelCPUCache L2 + L3Integrated GPUNPU
Ryzen AI Max+ 39516C / 32T; 3.0 GHz base; up to 5.1 GHz.80 MBRadeon 8060S; 40 CUs; up to 2.9 GHz.Up to 50 TOPS
Ryzen AI Max 39012C / 24T; 3.2 GHz base; up to 5.0 GHz.76 MBRadeon 8050S; 32 CUs; up to 2.8 GHz.Up to 50 TOPS
Ryzen AI Max 3858C / 16T; 3.6 GHz base; up to 5.0 GHz.40 MBRadeon 8050S; 32 CUs; up to 2.8 GHz.Up to 50 TOPS
PRO variants. AMD also supplies commercial Ryzen AI Max PRO parts with enterprise manageability and security features. They use the same principal Strix Halo architecture but are separate SKUs.
06

Shared platform specifications

AreaPublished specificationTechnical meaning
Process and packageTSMC 4 nm CPU and system dies; FP11; two or three dies.The CPU is chiplet-based; the 385 omits the second CPU chiplet.
Power range55 W default; 45–120 W configurable TDP.OEM cooling and firmware materially affect sustained clocks.
MemoryUp to 128 GB LPDDR5X-8000; 256-bit interface.256 GB/s is the theoretical raw rate at maximum memory speed.
Graphics memoryVariable Graphics Memory; up to 96 GB configurable.This is reserved system memory, not separate on-package HBM or GDDR.
PCI ExpressPCIe 4.0; 16 usable lanes.External expansion bandwidth is below current PCIe 5 desktop platforms.
Display and mediaDisplayPort 2.1, HDMI 2.1, AV1 encode/decode; up to four displays.Media functions are fixed-function blocks rather than CPU software paths.
AI totalUp to 126 overall TOPS on Max+ 395; NPU up to 50 TOPS.Overall TOPS combines unlike CPU, GPU and NPU engines and is not one executable pool.
07

Software paths

EnginePrimary software pathBest fit
Zen 5 CPUNative x86-64 applications; AVX-512; operating-system schedulers.Serial work, control flow, preprocessing and broad compatibility.
RDNA 3.5 GPUAMD Software drivers; DirectX, Vulkan, OpenCL and supported HIP/ROCm paths.Graphics, content creation and highly parallel local inference.
XDNA 2 NPURyzen AI Software with supported frameworks and compiled graphs.Qualified neural inference within the NPU’s operator and memory limits.
Video engineApplication media APIs and codecs.Decode and encode without consuming general shader or CPU resources.
08

Videos

VideoHotHardware · AMD Just Dropped A Monster Mini-PC: Meet Ryzen AI Halo | CES 2026YouTube ↗
VideoAI Master · AMD Just Killed AI Subscriptions Forever (Ryzen AI Halo)YouTube ↗
VideoLevel1Techs · Ryzen AI Halo Developer Workstation · from 14:35YouTube ↗
VideoLevel1Techs · Ryzen AI Halo Developer Workstation · from 13:56YouTube ↗
09

Terms

APU
A processor combining CPU and graphics functions.
CU
An RDNA graphics compute unit.
NPU
A specialised neural-processing engine.
TOPS
Trillion operations per second under a stated numeric format.
Unified memory
One physical memory pool addressable by multiple engines.
cTDP
An OEM-configurable processor power range.
Chiplet
One die combined with other dies in a package.
VGM
System memory reserved for the integrated GPU.
10

Limits of the evidence

  • Maximum clocks, 120 W operation and memory capacity depend on the OEM system.
  • Unified memory removes explicit copies in some paths but does not remove bandwidth contention.
  • “Up to 96 GB VRAM” is a configurable share of system memory, not dedicated VRAM.
  • TOPS values use different engines and data types; they do not predict model throughput by themselves.
  • ROCm and NPU application support varies by operating system, driver and framework version.
  • Price and vendor performance comparisons are excluded.
11

Primary sources

  1. Ryzen AI Max+ 395 specificationsCPU, memory, graphics, NPU, I/O and package data.
  2. Ryzen AI Max 390 specifications12-core model and Radeon 8050S configuration.
  3. Ryzen AI Max 385 specificationsEight-core, two-die model.
  4. Ryzen AI Max+ 395 developer platformMemory bandwidth, VGM and RDNA 3.5 details.
  5. CES 2025 product announcementSeries composition and launch context.