AMD technical article 005
Ryzen 9000 Series
How AMD’s AM5 desktop family uses Zen 5 CPU chiplets, a reusable I/O die and two forms of second-generation 3D V-Cache.01
What it is
Ryzen 9000 is AMD’s Zen 5 desktop processor family for the AM5 socket. Standard models range from six to 16 CPU cores. X3D models add vertically stacked L3 cache to reduce trips to external memory; the April 2026 Ryzen 9 9950X3D2 Dual Edition places that extra cache under both eight-core compute dies.
The design separates compute from I/O. One or two 4 nm core-complex dies contain the CPU cores and most cache. A 6 nm I/O die contains the DDR5 memory controllers, PCIe links, USB-related platform interfaces and a small integrated Radeon graphics engine. This lets AMD reuse one desktop platform while varying core count and cache.
CPU architectureZen 5Six to 16 cores
Package1–2 CCDs + I/O die4 nm compute; 6 nm I/O
PlatformSocket AM5DDR5 and PCIe 5.0
Cache ceiling208 MB total9950X3D2 Dual Edition
02
Why the design exists
Desktop workloads do not all need the same resource. Compilation and rendering scale with cores; games can be limited by memory latency; lightly threaded applications reward frequency. A common chiplet package allows AMD to assemble different balances without designing a separate monolithic die for each product.
| Design choice | Function | Trade-off |
|---|---|---|
| Separate CPU chiplets | Scale from one to two eight-core CCDs. | Traffic between CCDs crosses the package fabric. |
| Shared I/O die | Centralises DDR5, PCIe and platform functions. | Memory traffic from every core converges on the I/O die. |
| Large L3 cache | Keeps frequently reused data near cores. | Capacity is finite and access is not uniform across CCDs. |
| 3D V-Cache models | Add L3 without expanding the compute die’s footprint. | Benefits depend on workload locality; it does not add cores or memory bandwidth. |
03
Chiplet architecture
04
How an instruction reaches data
- Schedule a thread.The operating system assigns software to a Zen 5 core and, on dual-CCD parts, chooses a core complex.
- Predict and decode.Zen 5 fetches instructions, predicts control flow and feeds wider execution resources than Zen 4.
- Search local caches.L1, L2 and the CCD’s shared L3 are checked before a memory request leaves the compute die.
- Cross the package.A miss travels through Infinity Fabric to the I/O die’s memory controller.
- Access DDR5.The controller reads or writes system memory and returns data to the requesting CCD.
- Retire in order.Out-of-order execution completes work speculatively, then commits architectural results in programme order.
05
Principal retail line-up
| Model | Cores / threads | Boost / base | Total cache | TDP |
|---|---|---|---|---|
| Ryzen 9 9950X3D2 Dual Edition | 16 / 32 | Up to 5.6 / 4.3 GHz | 208 MB | 200 W |
| Ryzen 9 9950X3D | 16 / 32 | Up to 5.7 / 4.3 GHz | 144 MB | 170 W |
| Ryzen 9 9950X | 16 / 32 | Up to 5.7 / 4.3 GHz | 80 MB | 170 W |
| Ryzen 9 9900X3D | 12 / 24 | Up to 5.5 / 4.4 GHz | 140 MB | 120 W |
| Ryzen 9 9900X | 12 / 24 | Up to 5.6 / 4.4 GHz | 76 MB | 120 W |
| Ryzen 7 9800X3D | 8 / 16 | Up to 5.2 / 4.7 GHz | 104 MB | 120 W |
| Ryzen 7 9700X | 8 / 16 | Up to 5.5 / 3.8 GHz | 40 MB | 65 W |
| Ryzen 5 9600X | 6 / 12 | Up to 5.4 / 3.9 GHz | 38 MB | 65 W |
06
Platform specifications
| Area | Published capability | Interpretation |
|---|---|---|
| Socket | AM5, 1718-pin LGA. | Motherboard firmware must support the exact processor. |
| Memory | Dual-channel DDR5; ECC support depends on motherboard. | Rated transfer speed varies with DIMM count and configuration. |
| Expansion | PCIe 5.0 from the processor; chipset adds further I/O. | Lane routing and Gen 5 slot availability vary by board. |
| Overclocking | Unlocked multiplier; Precision Boost Overdrive and Curve Optimizer. | Operation beyond stock parameters depends on cooling and platform limits. |
| Integrated graphics | Two-core AMD Radeon Graphics on mainstream desktop SKUs. | Designed for display and basic graphics, not comparable with a discrete GPU. |
| Instruction set | x86-64 including AVX-512 support. | Applications must be compiled to use wider vector paths. |
07
Second-generation 3D V-Cache
| Arrangement | Cache placement | Operational consequence |
|---|---|---|
| 9800X3D | One CCD with 64 MB stacked cache beneath the compute die. | All eight cores on the processor access the enlarged L3 domain. |
| 9900X3D / 9950X3D | Stacked cache under one of two CCDs. | Software and firmware steer latency-sensitive threads towards the cache-rich CCD and frequency-sensitive work towards the other. |
| 9950X3D2 Dual Edition | Stacked cache beneath both CCDs. | All 16 cores have a local enlarged cache domain; cross-CCD data movement still exists. |
| Standard X models | No stacked cache. | Lower cache capacity; workload behaviour depends more heavily on ordinary L3 and DDR5. |
What cache does not do. Extra L3 reduces average memory access only when a workload reuses data that fits and maps well. It does not increase core count, DDR5 bandwidth or PCIe bandwidth.
08
Terms
- CCD
- A core-complex die containing Zen 5 cores and L3 cache.
- I/O die
- The die containing memory and external interfaces.
- SMT
- Two hardware threads exposed by each core.
- IPC
- Instructions completed per clock under a given workload.
- L3 cache
- Shared on-package memory below DRAM capacity but with lower latency.
- 3D V-Cache
- An additional SRAM die vertically bonded to a CCD.
- TDP
- A processor thermal-design operating point, not a universal power limit.
- Infinity Fabric
- AMD’s on-package data and control interconnect.
09
Limits of the evidence
- Boost clocks are maxima for eligible cores, not sustained all-core guarantees.
- TDP does not equal measured wall power and differs from peak package power.
- Memory speed, ECC, PCIe routing and overclocking depend on the motherboard.
- Cache-sensitive results vary with data set, thread placement and software.
- The 9950X3D2 Dual Edition is the current cache-capacity flagship, not automatically the fastest processor in every workload.
- The embedded CNET video summarises the 2024 launch keynote; it is not a technical specification source.
- Price and promotional benchmark comparisons are excluded.
10
Sources
- AMD Ryzen desktop processorsCurrent family and platform overview.
- Ryzen 9 9950X3D2 Dual Edition launchDual-cache architecture and April 2026 specifications.
- Ryzen 9000 Series technical overviewZen 5, AM5 and product structure.
- AMD Zen core architectureZen 5 front-end and execution changes.
- Original Ryzen 9000 announcementInitial line-up and platform capabilities.
- AMD’s 2024 Computex keynote in 12 minutesCNET video supplied for this article; launch context only.