AMD technical article 006
Instinct MI455X
How AMD’s CDNA 5 accelerator combines eight compute chiplets, 432 GB of HBM4 and open scale-up links for large AI training and inference systems.01
What it is
Instinct MI455X is AMD’s 2026 data-centre GPU accelerator for AI training, inference and high-performance computing. It uses the fifth-generation CDNA architecture, eight compute chiplets and 12 HBM4 stacks in a liquid-cooled embedded accelerator module.
The product is designed as one node in a larger system. Each accelerator provides 432 GB of high-bandwidth memory and direct scale-up links to peer accelerators. Servers then use PCIe-connected network interfaces for scale-out between nodes and racks. AMD’s Helios reference design arranges 72 MI455X accelerators as a rack-scale system; MI455X itself remains the accelerator module inside such systems.
ArchitectureCDNA 5Eight compute chiplets
Memory432 GB HBM423.3 TB/s peak bandwidth
Low-precision compute40.3 PFLOPS MXFP4Published peak matrix rate
Scale-up3.6 TB/s bidirectionalUALoE per accelerator
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Why it exists
Large models are constrained by several resources at once: arithmetic throughput, memory capacity, memory bandwidth and communication between accelerators. Adding matrix units alone cannot solve a model that does not fit in memory or a collective operation waiting on remote data.
| Workload pressure | Effect | MI455X response |
|---|---|---|
| Growing model state | Weights, gradients, optimiser state and KV cache exceed one device. | 432 GB HBM4 per accelerator and multi-accelerator partitioning. |
| Memory-bound kernels | Compute engines stall while data is fetched. | 12 HBM4 stacks deliver 23.3 TB/s published peak bandwidth. |
| Low-precision AI | Many inference and training stages tolerate fewer bits. | Native matrix paths for OCP MXFP4, MXFP6, MXFP8 and other formats. |
| Collective communication | Each partition must exchange activations, gradients or expert traffic. | UALoE scale-up links and PCIe-attached UALink/Ethernet scale-out interfaces. |
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Chiplet and memory architecture
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How a distributed layer executes
- Place the model.Software partitions weights and state across HBM4 pools when one accelerator cannot hold the complete workload.
- Fetch and stage data.HBM controllers feed the L2 cache and compute chiplets; the Tensor Data Mover handles supported multidimensional transfers.
- Execute matrix work.CDNA 5 engines apply the selected numeric format, such as BF16, FP8 or MXFP4.
- Reuse on package.L2 multicast can distribute common data to multiple compute regions without identical HBM reads.
- Synchronise peers.UALoE carries scale-up traffic between accelerator modules; split-named barriers coordinate producer and consumer work.
- Cross the cluster.PCIe-connected network interfaces move scale-out traffic between nodes or racks.
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From accelerator to rack
| Level | Composition | Published function |
|---|---|---|
| MI455X EAM | One liquid-cooled accelerator; eight XCDs; 432 GB HBM4. | Local compute, memory and direct scale-up links. |
| Compute tray | Four MI455X modules in the Helios reference design. | Serviceable accelerator building block with local scale-up connectivity. |
| Helios rack | 72 MI455X, AMD EPYC “Venice” CPUs and Pensando “Vulcano” AI NICs. | Reference architecture for rack-scale training and inference. |
| Multi-rack cluster | Multiple racks joined through an external scale-out fabric. | Expands model and data parallelism beyond one scale-up domain. |
Reference design, not one mandatory product. AMD states that Helios is a rack-scale design for partners to implement. Final systems, topology, cooling and network configuration depend on the manufacturer or cloud operator.
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Principal specifications
| Area | Published MI455X specification | Reading |
|---|---|---|
| Transistors and process | 320 billion; TSMC 2 nm and 3 nm FinFET. | Multiple process nodes are combined in one advanced package. |
| Compute organisation | Eight XCDs; 256 work-group processors; Wave32. | Thread groups execute across many independently scheduled compute regions. |
| HBM | 432 GB HBM4; 12 stacks; 23.3 TB/s peak. | Capacity and raw bandwidth are per accelerator. |
| Cache | 192 MB L2. | Shared on-package reuse layer below HBM capacity. |
| MXFP4 matrix | 40.3 PFLOPS peak. | Applies only to supported four-bit OCP microscaling operations. |
| MXFP6 / MXFP8 / FP8 matrix | 20.1 PFLOPS peak. | Higher precision halves the cited MXFP4 operation rate. |
| BF16 / FP16 matrix | 5.0 PFLOPS peak. | Common training formats with materially lower nominal operation count. |
| FP64 matrix | 5.0 TFLOPS peak. | Scientific double precision is a separate performance regime. |
| Clock | Up to 2.4 GHz engine clock. | A maximum, not a guaranteed sustained frequency. |
| Scale-up | 3.6 TB/s bidirectional UALoE per accelerator. | Aggregate link bandwidth, not usable payload throughput. |
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Mechanisms that change utilisation
| Mechanism | Function | Why it matters |
|---|---|---|
| Tensor Data Mover | Moves multidimensional tensor regions independently of arithmetic units. | Overlaps data movement with compute and reduces address-generation work. |
| L2 multicast | Delivers one cached data block to multiple compute destinations. | Reduces duplicated HBM traffic for shared operands. |
| WGP clustering | Coordinates groups of work-group processors. | Provides a larger cooperation domain for tiled kernels. |
| Split-named barriers | Separates arrival and wait operations. | Enables more flexible producer-consumer pipelines. |
| Microscaling formats | Share scaling metadata across blocks of low-bit values. | Reduces storage and arithmetic cost while retaining more range than a simple fixed scale. |
| ROCm software | Compilers, libraries, runtimes and framework integrations. | Hardware peaks are unreachable without supported kernels and communication software. |
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Terms
- XCD
- An accelerator compute die containing CDNA execution resources.
- FCD
- A fabric and cache die connecting compute and memory paths.
- HBM4
- Stacked high-bandwidth memory adjacent to the processor package.
- WGP
- A work-group processor that schedules groups of GPU threads.
- Wave32
- A group of 32 threads executing one instruction stream.
- MXFP
- An OCP block-scaled low-precision numeric format.
- UALoE
- UALink carried over an Ethernet physical layer for scale-up communication.
- EAM
- An embedded accelerator module used in liquid-cooled systems.
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Limits of the evidence
- MI455X is newly launched; published specifications and architecture details currently come primarily from AMD.
- Peak FLOPS assume a particular data type, operation and sparsity rule; unlike formats are not directly comparable.
- HBM and link figures are raw peak rates, not measured application throughput.
- Helios figures describe a reference design; partner systems may differ.
- AMD publications show differing per-GPU HBM bandwidth in some system-level materials; this article uses the 23.3 TB/s MI455X product specification.
- The embedded APT video provides launch context; it is not a technical specification source.
- Availability, price and vendor benchmark claims are excluded.
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Sources
- AMD Instinct MI455X product pageCompute, memory, link, packaging and software specifications.
- AMD Instinct MI400 SeriesSeries architecture and deployment context.
- AMD CDNA architectureCDNA 5 execution, memory and data-movement mechanisms.
- AMD Helios rack-scale reference design72-accelerator topology, rack composition and aggregate figures.
- ROCm documentationProgramming model, libraries and framework support.
- AMD AI chips, MI455 and OpenAI partnershipAPT video supplied for this article; launch context only.